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Graph placement methodology accelerates chip design
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From the addendum to 'A graph placement methodology for fast chip design' in September 2024, co-authored by Jeff Dean. https://x.com/AndrewCurran_/status/21017…
Casper Hansen@casper_hansen_Sep 19
NEVER thought i would hear this from jeff dean he thinks we can compress chip design from 2 years to 3 months with RL + new EDA tooling essentially just by a specialized auto research loop for hardware!
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